In general, the present invention relates to a logic dividing method for assigning logic circuits to a module with a plurality of programmable large-scale integrated circuits (LSIs) mounted thereon and relates to a module wiring technology in a logic emulation system for verifying performance and operations of the large-scale integrated circuits. More particularly, the present invention relates to an effective technology applicable to a logic dividing and module wiring system which takes a positional relation with an external interface of a module and operation timings into consideration.
In development of a large-scale integrated circuit which is referred to hereafter as an LSI, it is important that as many defects as possible are detected before a prototype is built. This is because, if a defect is detected after a prototype is built, it will take time to determine a cause of the defect. In addition, since the prototype must be rebuilt if a defect is detected, it is feared that the cost and the development time will increase.
As a solution to the problem, there is logic emulation using a field programmable gate array (which is referred to hereafter as an FPGA) for a programmable large-scale integration circuit. In the logic emulation, a logic circuit to be verified is programmed by using an FPGA and logic of the circuit is verified by actually operating the FPGA in conjunction with an actual product sold in the market or an existing LSI.
In addition, with logic of a logic circuit to be processed becoming large in scale in recent years, the logic circuit is divided into a plurality of FPGAs each serving as a target of circuit implementation. Then, the FPGAs are assembled for carrying out logic emulation.
As logic emulation apparatus for carrying out such logic emulation, there is a technology disclosed in Japanese Patent Laid-open No. Hei 6-3414. According to this technology, logic emulation is carried out by using a module which is called a pseudo LSI and comprises a plurality of FPGAs, a non-volatile memory for storing data of a logic circuit to be verified, a transfer unit for transferring data between the FPGAs and the non-volatile memory and a power supply. As a method to implement such a module, a plurality of FPGAs are mounted on the module as bare chips. Such a module is referred to as a multi-chip module.
In addition, as a typical technique for carrying out logic emulation whereby a logic circuit is divided, being targeted at a plurality of FPGAs and the FPGAs are assembled, a technology is disclosed in a document such as Japanese Patent Laid-open No. Hei 10-312309. As a technique for dividing a logic circuit into a plurality of portions, a technology is disclosed in Japanese Patent Laid-open No. Hei 8-212249.
By referring to a flowchart shown in FIG. 25, the following description briefly explains work and processing to generate logic data for logic emulation which uses a logic emulation apparatus disclosed in Japanese Patent Laid-open No. Hei 6-3414, and adopts the logic-emulation technique disclosed in Japanese Patent Laid-open No. Hei 10-312309 as well as the logic-circuit dividing technique disclosed in Japanese Patent Laid-open No. Hei 8-212249.
As shown in FIG. 25, the flowchart begins with a step S2501 at which a logic circuit subjected to logic emulation is input. Then, at the next step S2502, the logic circuit input at the step S2501 is divided, being targeted at a plurality of FPGAs. That is to say, results of the division are each assigned to one of the FPGAs. Then, at the next step S2503, the FPGAs are wired on a module for programming the logic circuit input at S2501. In actuality, since wiring on the module has been done, pins of each of the FPGAs are associated with logic signals. Then, at the next step S2504, in accordance with results of assignment of portions resulting from the division of the logic circuit at the step S2502 to the FPGAs and pin positions determined at the step S2503, placement and wiring of the FPGAs are carried out to create logic data. Finally, at the step S2505, logic emulation is carried out by programming the logic data created at the step S2504 on the FPGAs on the module.
As one of problems encountered in such logic emulation, in a module where the LSI under development and the logic circuit are programmed to operate, the package size, the connection structure and the pin layout vary. Thus, there is raised a problem of a need to individually create both a board for mounting an LSI to be developed and a board for mounting the module described above.
It takes time to create a board for mounting the module described above. In addition, the logic circuit which is programmed on the module and serves as an object of logic verification needs to be connected to another LSI to be actually operated in conjunction with the logic circuit. Thus, the board is created concurrently with the work to design and to divide the logic circuit in many cases. For these reasons, at a point of time the logic circuit is divided, external interface signals of the logic may have been assigned to pins of each connector on the module or assigned to connectors at a connector level even if not assigned to pins of each of the connectors.
In the conventional technology described above, however, the design of a board is not taken into consideration when the logic circuit is divided. Thus, a variety of problems are raised in implementing the logic emulation.
For example, the conventional technology does not consider which connector on the module external interface signals of the logic are to be assigned to when the logic circuit is divided. As a result, there is raised a problem of unavoidable diversion of logic related to external interface signals independent of results of the division and the assignment of the external interface signals to connector pins.
This problem is described in concrete terms as follows. The module described in Japanese Patent Laid-open No. Hei 6-3414 comprises a connector, FPGAs, wires connecting the connector to one or more FPGAs and wires connecting two or more FPGAs.
With an external interface signal assigned to a wire connecting a connector to two or more FPGAs, the external interface signal is propagated to pins of all the FPGAs connected to the connector by the wire. Thus, a pin of any of the FPGAs not logically using the external interface signal becomes unnecessary and other necessary logic signals can not be assigned. If a number of such wires are used, the number of virtually usable pins in each FPGA becomes small. Thus, the number of wires connecting a connector pin to an FPGA on a 1-to-1 basis increases. This holds true of wires connecting an FPGA to another. With a connector pin connected to an FPGA on a 1-to-1 basis, it is desirable to assign logic related to an external interface signal assigned to a connector pin to an FPGA connected to the connector pin if the operating speed of the logic or a wire resource on the module is taken into consideration.
To put it more concretely, assume that external interface signals A and B have been assigned to two pins of a connector directly connected to the same FPGA on the module. In this case, it is desirable to assign logic related to the external interface signals A and B to the FPGA directly connected to the connector as described above.
Since the positions of connector pins are not taken into consideration when logic is divided in accordance with the conventional technology described above, the external interface signals A and B may be assigned to different FPGAs in some cases. In this case, one of the external interface signals A and B is connected directly to logic in another FPGA from a connector by way of an FPGA directly connected to the connector. As a result, there is raised a problem of a reduced operating speed.
In addition, the following problem is also raised. If a logic circuit is divided, a critical-delay path may also be divided into segments assigned to a plurality of FPGAs in some cases. A path is a route of propagation of a signal in logic. For example, a path starts at a flip-flop and ends at another flip-flop, comprising a net and gates through which a signal is propagated. In this case, it is desirable to assign the net between FPGAs which serves as an element of a critical-delay path to a wire directly connecting the FPGAs as a first priority. According to the conventional technology, however, a delay is not taken into consideration in the wiring work. Thus, a wire directly connecting two FPGAs can not be used as a critical-delay path passing through the FPGAs. That is to say, the critical-delay path passing through the two FPGAs must be implemented by a wire connecting the two FPGAs by way of another FPGA. As a result, there is raised a problem of a reduced operating speed in some cases.
It is thus an object of the present invention addressing the problems described above to provide a logic dividing and module wiring system for operating logic related to external interface signals and interface signals among circuits obtained as a result of division or a logic circuit at a high speed.
The applicant for a patent of the present invention has completed separate patent application processes, namely, Japanese Patent Laid-open No. Hei 10-161813 in Japan and a U.S. patent application Ser. No. 09/328,800 in the US, for an invention solving the problem of a need to individually create both a board for mounting an LSI to be developed and a board for mounting the module for logic emulation. The invention according to the above completed applications provides a means for carrying out logic emulation. The means is provided with a module, a module connector serving as a connection facility for the module and a terminal land for mounting an LSI under development. On one surface or both the surfaces of the module, there are mounted at least an FPGA used for implementing logic operations by programming logic data and at least one switch device allowing connections among circuits to be programmed. The module connector is used for electrically connecting the module to an external device. The module includes wires directly connecting the FPGAs to the module connector and wires connecting FPGAs to the module connector through the switch devices. The means carries logic emulation by using a board connected to the terminal land using a board connector on a 1-to-1 basis and actually mounting an LSI under development on the board by connecting the module connector to the board connector.
A problem of logic related to an external interface signal not operating on the module at a high speed may be raised when a logic emulation technique according to the conventional technology is adopted in implementation of the module according to the conventional technology and the module in a process of application for a patent as described in Japanese Patent Laid-open No. Hei 10-161813. In order to solve this problem, the logic dividing and module wiring system provided by the present invention employs the following means.
First of all, the present invention presents a logic emulation system for operating a logic circuit through execution of the steps of:
using a module on which a plurality of FPGAs and a plurality of input/output connectors are mounted and interconnected directly or through switch devices by wires in advance like the one disclosed in Japanese Patent Laid-open No. Hei 10-161813;
dividing the logic circuit into a plurality of circuits;
assigning each of the circuits obtained as a result of the division of the logic circuit to one of the FPGAs; and
assigning interface signals among the circuits obtained as a result of the division of the logic circuit to wires on the module,
wherein extracted pieces of logic are assigned to FPGAs connected directly to pins of the connectors on the module on the basis of first information, second information and third information where:
the first information is information on assignments of external interface signals of logic to the connectors;
the second information is information on logic related to the external interface signals of logic; and
the third information is information on wires connecting the connectors to the FPGAs on the module.
It should be noted that, in order to determine the assignment of external interface signals of logic to connector pins, as information on a board on which the module is to be mounted, typically, a net list of the board is acquired, and external interface signals of logic connected to the same part on the module are grouped and assigned to the same connector. In addition, for each external interface signal, as information on priority of pin assignment, criticality is acquired to be used typically as an indicator as to how critical a delay is and the assignment of connector pins is determined on the basis of the criticality of the delay.
Furthermore, in order to obtain information on logic related to external interface signals, logic using the external interface signals on the logic circuit is traced by using gate definition information describing, among other data, connection of each gate on the logic circuit. An example of the gate definition information is a gate library. A result of the tracing can also be used as the second information.
Moreover, for a net spread over a plurality of FPGAs as a result of logic division, a delay of an external interface signal between FPGAs of a net is computed for each net and wiring of the module is carried out in accordance with the criticality of each delay.
In the division of a logic circuit according to a logic dividing method provided by the present invention, an associative relation determining assignments of external interface signals of logic to connector pins in advance is acquired and pieces of logic related to the external interface signals are assigned to FPGAs which are wired to connector pins on a 1-to-1 basis. Thus, an external interface signal does not pass through an unrelated FPGA along a path starting from a connector pin and ending at an FPGA to which logic related to the external interface signal is assigned. As a result, the logic emulation can be carried out at a high speed.
In addition, according to the logic dividing method provided by the present invention, wiring is carried out in accordance with a priority order determined by the criticality of a transmission delay incurred by an interface signal propagating along each of paths each connecting a plurality of FPGAs to each other with the highest priority assigned to the most critical delay. As a result, a path with a critical transmission delay does not pass through an unnecessary FPGA, making it possible to operate the module at a high speed.
As described above, when a logic circuit is divided in accordance with the present invention,
an assignment reading means reads in assignments of external interface signals of logic to connector pins;
logic extracting means extracts pieces of logic related to the external interface signals of the logic; and
the pieces of logic extracted by the logic extracting means are assigned to FPGAs directly connected to the connector pins in accordance with the assignment of the external interface signals of the logic to the connector pins read in by the assignment reading means.
By doing so using the means described above, logic which is programmed on a module and related to an external interface signal can be operated at a high speed.
In addition, there are also provided:
a means for checking delays after dividing a logic circuit and determining criticality of each of the delays according to a priority order of interface signals between FPGAs; and
a means for implementing wiring on a module in accordance with the criticality of each of the delays.
Thus, it is possible to prevent a slowdown of the operation of an interface signal between FPGAs which serves as an element of a path with a critical delay. As a result, the logic emulation can be operated at a high speed.